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Timing Diagrams V
A+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0– D15
outputs. (Continued)
8: RD pulse width
9: RD high to next RD or WR low
11: WR pulse width
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
V
A+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0– D15 outputs.
22: INT high from RD low
23: DMARQ low from RD low
DS011264-17
FIGURE 11. Non-Multiplexed Data Bus (ALE = 1)
DS011264-18
FIGURE 12. Interrupt and DMARQ
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